1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of controlling the same.
2. Description of the Related Art
Nonvolatile semiconductor memory devices (nonvolatile memories) are used as large-capacity and small-size information recording media, in a variety of fields such as computers, communication and measurement devices, automatic controllers, and appliances used around individuals. In addition, application software used in the above computers employs data-rewritable nonvolatile memories because it can desirably fix bugs and can be upgraded. The nonvolatile memories include a flash memory, and a RRAM (Resistive Random Access Memory).
The configuration and action of each of the flash memory and RRAM will be described.
First, the flash memory will be described. The flash memory includes an ETOX (registered trademark of U.S. Intel Corporation) flash memory.
Here, FIG. 8 shows a schematic constitution example of a memory cell array AT of the ETOX flash memory, and the memory cell array AT is composed of a plurality of memory cells (ETOX cells). The memory cell array AT shown in FIG. 8 is configured such that m×n ETOX cells MT are arranged in the form of a matrix, and gate terminals of the memory cells MT on the same row are connected to the same word line WLi (i=1 to m, m=2048, for example), and drain terminals of the memory cells MT on the same column are connected to the same bit line BLj (j=1 to n, n=512, for example), and source terminals of all the memory cells MT are connected to a common source line SL. The ETOX flash memory further has a row decoder which applies a voltage to the word line WLi (i=1 to m) based on a row address signal, a column decoder which applies a voltage to the bit line BLj (j=1 to n) based on a column address signal, and an erasing circuit which applies a high voltage Vpp (12V, for example) to the source line SL based on an erasing signal, which are provided as peripheral circuits of the memory cell array AT.
FIG. 9 shows the configuration of the ETOX cell as the memory cell in the ETOX flash memory. As shown in FIG. 9, the ETOX cell is composed of a source 103 and a drain 102 formed in a semiconductor substrate 101 and having a polarity different from that of the semiconductor substrate 101, and a gate insulation film 104 formed on the semiconductor substrate 101, and a floating gate 105, an interlayer insulation film 106, and a control gate 107 formed on the gate insulation film 104 above a region sandwiched between the drain and the source.
A descriptions will be briefly made of each action of programming, reading, and erasing of the ETOX cell. In addition, here, it is assumed that when a threshold voltage of the memory cell is high, its state is a programmed state “0”, and when the threshold voltage of the memory cell is low, its state is an erased state “1” in the flash memory.
First, the programming action of the ETOX cell MT will be described. The programming action for the ETOX cell MT is performed by applying a low source voltage Vs (0V, for example) to the source 103, a drain voltage Vd (6V, for example) higher than the source voltage Vs, to the drain 102, and a high gate voltage Vg (12V, for example) to the control gate 107, in the programming target cell MT which is a memory cell MT to be programmed. At this time, a hot electron is generated at the region sandwiched between the source and drain in the semiconductor substrate 101, and injected to the floating gate, whereby the threshold voltage of the ETOX cell is raised.
In addition, since programming characteristics vary in the memory cell such as the ETOX cell due to variation in production process, a programming verifying action is performed to verify whether or not the threshold voltage of the programming target cell MT is not less than a predetermined programming verifying threshold value Vthp (5.3V, for example). The programming verifying action is performed by applying a voltage to the programming target cell MT and a reference cell whose threshold voltage is the programming verifying threshold voltage under a predetermined programming verifying voltage condition, and when it is verified that the threshold voltage of the programming target cell MT is not less than the threshold voltage of the reference cell, it is verified that the programming action has been normally completed. When it is verified that the programming action has not been normally completed, a re-programming action and a programming verifying action after the re-programming action are performed. In addition, when it is verified that the programming action has been normally completed after the re-programming action, it is confirmed whether or not the programming target cell MT is in a programming excess state by comparing its threshold voltage with a programming excess verifying threshold voltage.
Next, the reading action for the ETOX cell MT will be described. The reading action of the ETOX cell MT is performed by applying a low source voltage Vs (0V, for example) to the source 103, a drain voltage Vd (1V, for example) a little higher than the source voltage Vs to the drain 102, and a gate voltage Vg (5V, for example) higher than the drain voltage Vd, to the control gate 107 in the reading target cell MT which is a memory cell MT to be read, and it is verified whether the reading target cell MT is in the programmed state or the erased state, based on the amount of the current flowing between the source and drain of the reading target cell MT. More specifically, when the value of the current flowing between the source and drain of the reading target cell MT is smaller than a predetermined verifying current value, the programmed state “0” is determined and when it is larger than the verifying current value, the erased state “1” is determined.
Next, the erasing action for the ETOX cell MT will be described. The erasing action of the ETOX cell MT is performed by applying a high source voltage Vs (12V, for example) to the source 103, and a low gate voltage Vg (0V, for example) to the control gate 107 and keeping the drain 102 in a floating state, in the erasing target cell MT which is a memory cell MT to be erased. At this time, a fowler-nordheim current flows between the floating gate and source through the tunnel oxide film 104 of the erasing target cell MT and electrons are withdrawn from the floating gate 105 and the threshold voltage of the erasing target cell MT is lowered.
After the erasing action, an erasing verifying action is performed to verify whether or not the threshold voltage of the erasing target cell MT is not more than an erasing verifying threshold voltage V the (3.1V, for example). The erasing verifying action is performed by applying a voltage to the erasing target cell MT and a reference cell whose threshold voltage is the erasing verifying threshold voltage under a predetermined erasing verifying voltage, and when it is verified that the threshold voltage of the erasing target cell MT is not more than the threshold voltage of the reference cell, it is verified that the erasing action has been normally completed. When it is verified that the erasing action has not been normally completed, a re-erasing action and an erasing verifying action after the re-erasing action are performed.
Meanwhile, since the erasing speed of the erasing action is 0.6 to 1 second in general, it is lower than the programming speed of the programming action. Therefore, the erasing action is performed by the block composed of a plurality of, for example, 64 k bytes of memory cells in an actual device.
Next, the RRAM will be described. The RRAM is a resistive nonvolatile memory using a variable resistive element whose electric resistance is changed reversibly in response to the application of a voltage pulse.
Here, FIG. 10 shows a schematic configuration example of a memory cell array AR of the RRAM, and the memory cell array AR includes a plurality of memory cells MR. The memory cell MR, is composed of one transistor T and one variable resistive element R, and one end of the variable resistive element R is connected to a drain terminal of the transistor T. The memory cell array AR shown in FIG. 10 is configured such that m×n memory cells MR are arranged in the form of a matrix, gate terminals of the transistors T on the same row are connected to the same word line WLi (i=1 to m), the other ends of the variable resistive elements R on the same column are connected to the same bit line BLj (j=1 to n), and source terminals of all the memory cells MR are connected to a common source line SL. The RRAM further has a row decoder which applies a voltage to the word line WLi (i=1 to m) based on a row address signal, a column decoder which applies a voltage to the bit line BLj (j=1 to n) based on a column address signal, and an erasing circuit which applies a voltage to the source line SL based on an erasing signal, which are provided as peripheral circuits of the memory cell array AR.
FIG. 11 shows a schematic configuration example of the variable resistive element R. As shown in FIG. 11, the structure of the variable resistive element R is extremely simple such that a lower electrode 211, a variable resistor 212, and an upper electrode 213 are laminated in this order. The resistance value of the variable resistive element R can be reversibly changed by applying a voltage pulse between the upper electrode 213 and the lower electrode 211. Data can be stored by changing the resistance state by this reversible resistance changing action (referred to as the switching action” occasionally hereinafter). In addition, here, a description will be made assuming that when the variable resistive element R is in a low resistance state, its state is in a programmed state, and when the variable resistive element R is in a high resistance state, its state is an erased state.
FIG. 12 is a cross-sectional schematic view of one memory cell MR in the memory cell array AR shown in FIG. 10. As described above, the one memory cell MR is composed of the transistor T and the variable resistive element R.
The transistor T is composed of a gate insulation film 203 and a gate electrode 204 laminated on a semiconductor substrate 201, and a drain diffusion region 205 and a source diffusion region 206 formed in the semiconductor substrate 201, and an element isolation region 202 to electrically isolate the transistors T is formed between the transistors T. In FIG. 12, a first interlayer insulation film 207 made of BPSG (Boron Phosphorous Silicate Glass) is formed on the semiconductor substrate 101 and the transistor T.
The variable resistive element R is formed on the first interlayer insulation film 207 in FIG. 12, and similar to FIG. 11, composed of the lower electrode 211 composed of a TiN film 211b having a thickness of 100 nm and a Ti film 211a having a thickness of 50 nm, the variable resistor 212 composed of a cobalt oxide having a thickness of 5 to 50 nm, and the upper electrode 213 composed of a Ta film having a thickness of 100 nm, which are laminated in this order. In addition, the lower electrode 211 is electrically connected to the drain diffusion region 205 of the transistor T through a contact electrode 208 made of conductive metal. In addition, the variable resistor 212 may be composed of a nickel oxide or tantalum oxide, or an oxide of transition metal element such as an zinc oxide or niobium oxide, instead of the cobalt oxide. In addition, the lower electrode 211 and the upper electrode 213 may be composed of a titanium nitride or materials such as Pt, Ir, Os, Ru, Rh, Pd, Al, and W. In FIG. 12, a second interlayer insulation film 209 having a thickness of 50 to 60 nm is formed on the first interlayer insulation film 207 and the variable resistive element R.
Furthermore, referring to FIG. 12, the gate electrode 204 of the transistor T serves as the word line WLi. In addition, a source line wiring 215 serving as the source line SL is made of TiN/Al—Si/TiN/Ti and formed on the second interlayer insulation film 209, and electrically connected to the source diffusion region 206 of the transistor T through a contact electrode 214. In addition, a bit line wiring 217 serving as the bit line BLi is formed on the second interlayer insulation film 209 and electrically connected to the upper electrode 213 of the variable resistive element R through a contact electrode 216. In addition, a third interlayer insulation film 218 is formed on the source wiring 215, the bit line wiring 217 and the second interlayer insulation film 209, a fourth interlayer insulation film 219 is formed on the third interlayer insulation film 218, a surface protection film 220 is made of a SiN film on the fourth interlayer insulation film 219.
As shown in FIG. 12, since the transistor T and the variable resistive element R are arranged in series, the transistor T of the memory cell MR selected by the voltage change of the word line WLi is turned on, and only the variable resistive element R of the memory cell MR selected by the voltage change of the bit line BLi can be programmed or erased selectively.
Hereinafter, a description will be made of each action of programming, reading, and erasing. In addition, the description will be made of a case where the structure and the material of the variable resistive element R are provided so that its characteristics become asymmetric, and voltage pulses having different polarities are applied between the programming action and the erasing action.
First, a description will be made of the programming action of the variable resistive element R in the memory cell MR. To perform the programming action of the variable resistive element R, a predetermined programming row voltage, 2V, for example is applied to the word line WLi (i=1 to m) connected to the programming target cell MR which is a memory cell MR to be programmed, and 0V is applied to the word line WLi other than the word line WLi connected to the programming cell MR. In addition, a predetermined programming column voltage, 2V, for example is applied to the bit line BLj (j=1 to n) connected to the programming target cell MR, and 0V is applied to the bit line BLj other than the bit line BLj connected to the programming target cell MR. Furthermore, 0V is applied to the source line SL. In addition, the programming row voltage applied to the word line WLi connected to the programming target cell MR is set so as to be higher than a value (threshold voltage value of the switching action) which causes the resistance value of the variable resistive element R to be changed by a voltage difference between both ends of the variable resistive element R so that the variable resistive element R becomes the low resistance state.
Thus, the voltage having the positive polarity is applied to the variable resistive element R of the programming target cell MR, and the resistance value is reduced and the low resistance state is implemented. In addition, the voltage is not applied to the non-programming target cell MR other than the programming target cell MR, so that the programming is not performed therein.
In addition, since the programming characteristics vary due to the variation in production process in the RRAM memory cell MR similar to the ETOX cell, a programming verifying action is performed after the programming action.
Next, a description will be made of the reading action of the variable resistive element R in the memory cell MR. To perform the reading action in the variable resistive element R, a predetermined reading row voltage, 2V, for example is applied to the word line WLi (i=1 to m) connected to the reading target cell MR which is a memory cell MR to be read, and 0V is applied to the word line WLi other than the word line WLi connected to the reading target cell MR. In addition, a predetermined reading column voltage, 0.7V, for example is applied to the bit line BLj (j=1 to n) connected to the reading target cell MR, and 0V is applied to the bit line BLj other than the bit line BLj connected to the reading target cell MR. Furthermore, 0V is applied to the source line SL. In addition, the reading row voltage applied to the word line WLi connected to the reading target cell MR is set such that the voltage difference between both ends of the variable resistive element R is smaller than the threshold voltage value of the switching action so that the resistance value of the variable resistive element R is not changed.
When the variable resistive element R of the reading target cell MR is in the low resistance state, the value of the current flowing in the memory cell MR is large, and when the variable resistive element R is in the high resistance state, the value of the current flowing in the memory cell MR is small, so that the state of the memory cell can be detected by detecting the value of the current flowing in the memory cell MR.
Next, a description will be made of the erasing action of the memory cell MR. To perform the erasing action in the variable resistive element R, a predetermined erasing row voltage, 2V, for example is applied to the word line WLi (i=1 to m) connected to the erasing target cell MR which is a memory cell MR to be erased, and 0V is applied to the word line WLi other than the word line WLi connected to the erasing target cell MR. In addition, 0V is applied to the bit line BLj (j=1 to n) connected to the erasing target cell MR, and 2V is applied to the bit line BLj other than the bit line BLj connected to the erasing target cell MR. Furthermore, a predetermined source voltage, 2V, for example is applied to the source line SL.
Thus, the voltage having the negative polarity is applied to the variable resistive element R of the erasing target cell MR, and the resistance value is increased and the high resistance state is implemented. In addition, the voltage is not applied to the variable resistive element R of the non-erasing target cell MR other than the erasing target cell MR, so that the erasing action is not performed. In addition, the erasing row voltage applied to the word line WLi connected to the erasing target cell MR is set so that the transistor T of the erasing target cell MR is turned on, and the source voltage applied to the source line SL is set so that the voltage difference between both ends of the variable resistive element R of the erasing target cell MR becomes larger than the threshold voltage value of the switching action.
In addition, although the description has been made of the case where the voltage pulses having different polarities are applied between the programming action and the erasing action in the RRAM, as another method of changing the resistance value of the variable resistive element R in the memory cell MR of the RRAM, voltage pulses having different pulse widths may be applied between the programming action and the erasing action.
In addition, still another method of changing the resistance value of the variable resistive element R in the memory cell MR of the RRAM includes a nonvolatile semiconductor memory device in which the value of a variable resistive element R of a memory cell MR is changed by switching the load resistance characteristics of a load circuit such as a row decoder, a column decoder, a load resistance characteristics variable circuit, and a synthetic circuit such as parasitic resistance of a signal wiring connecting the above circuits, between at the time of programming action and at the time of erasing action (refer to U.S. Pat. No. 7,433,222, for example).
The above nonvolatile semiconductor memory device is configured such that the load resistance characteristics variable circuit is provided between a voltage generating circuit and the row decoder, and the load resistance characteristics of the load circuit electrically connected to a selected memory cell in series are switched between at the time of programming action and at the time of erasing action. In addition, detailed principle and action are described in the above patent document.
Meanwhile, the programming speed and the erasing speed of the RRAM are several tens of nanoseconds when a voltage of 1.5V to 3V is applied to the variable resistive element R, which is higher than those in the flash memory. Therefore, the erasing action of the RRAM is not necessarily performed by the block and can be performed by the bit unlike the flash memory. Thus, similar to the RRAM disclosed in the above patent document, the programming action, the reading action, and erasing action can be performed in the same cycle in the RRAM in which the programming action and the erasing action can be performed at the same time.
Recently, since the capacity of application software or data tends to increase, it is desired to speed up the writing action of the data in the nonvolatile memory such as the above flash memory and RRAM.
In addition, some flash memories have the burst function that executes the programming actions continuously by a plurality of programming commands, so that a time taken for the programming actions is increased as a whole, in proportion to the number of programming commands in the burst function in the flash memory. In this case, as described above, since the capacity of the application software and data tends to increase, the number of programming commands in the burst function tends to increase, and it is considered that the time taken for the writing actions as is considerably increased as a whole in the future. Therefore, it is desired to reduce the time taken for the writing actions in the flash memory having the burst function especially.
Meanwhile, a time taken for the writing action is shorter in the RRAM than the flash memory. However, similar to the flash memory, when the RRAM has the burst function, it is expected that the time taken for the writing actions is increased as a whole in the future because the capacity of the application software and data tends to increase. Therefore, similar to the flash memory, the time taken for the writing action is desirably reduced in the RRAM having the burst function.